module	div_50m(
	input		wire			clk,
	input		wire			res_n,
	
	output	    reg			    clk_1_sec,
    output      reg             led
);
	
	parameter	F_clk = 26'd50_000_000;
	reg[25:0]	cnt;
	
	always@(posedge clk or negedge res_n)begin
        if(~res_n)begin
            cnt <= 26'd0;
        end
        else begin
            if(cnt == F_clk-1)begin
                cnt <= 26'd0;
            end
            else begin
                cnt <= cnt + 1'd1;
            end
        end
	end
	
	always@(posedge clk or negedge res_n)begin
        if(~res_n)begin
            clk_1_sec <= 1'b0;
            led <= 1'b0;
        end
        else begin
            if(cnt == 26'd0)begin
                clk_1_sec <= 1'b1;
                led <= ~led;
            end
            else begin
                clk_1_sec <= 1'b0;
                led <= led;
            end
        end
	end

endmodule
